1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor integrated circuit, and more particularly, to an isolation method in the fabrication of a semiconductor device.
2. Description of the Related Art
To meet the demands of fabricating highly integrated semiconductor devices, much research is currently being conducted into isolation methods. The isolation of active regions of the semiconductor device is performed using either a trench isolation method, by which a trench is formed in an inactive region between the active regions and an insulating material is filled into the trench, or a local oxidation of silicon (LOCOS) method by which a field oxide layer is formed on the inactive region, typically a poly-Si buffered LOCOS (PBL) method using the LOCOS principle.
Meanwhile, the LOCOS isolation method is improved to be suitable for fabricating a highly-integrated semiconductor device having a design rule below 0.35 .mu.m. The typical methods are poly encapsulated local oxidation (PELOX) disclosed in IEEE Trans. in ED, Vol. 39 No. 5 (1992) by Scott S. Roth et al., and poly-Si spacer (PSL) LOCOS disclosed in IEDM Tech Dig., p. 679 (1994) by D. H. Ahn et al.